In a variety of consumer electronics and computers, solid state data storage devices incorporating non-volatile memories (NVMs) are frequently replacing or supplementing conventional rotating hard disk drives for mass storage. As NVM speed and complexity increases, the need becomes greater for improved error correction and training of NVMs and NVM interfaces.
The use of error correction for memories, such as cyclic redundancy check (CRC), is known in the art and has been particularly useful for volatile memories, such as dynamic random access memory (DRAM). However, a number of limitations and drawbacks exist for implementing existing CRC techniques for NVM technologies. One such limitation is that CRC may introduce substantial latency in a memory circuit. While CRC is typically performed on every DRAM read operation, using such a configuration for NVMs may significantly slow down memory operations. Additionally, unlike DRAM technologies, which typically operate using either high-speed or zero-speed data transfer rates, NVM technology is typically configured to operate at a wide range of speeds and is typically configured to be backward compatible for lower-speed transfer rates.
In addition, NVMs are currently equipped with NVM controllers that are operative to “train” or calibrate the NVM and/or NVM interfaces to detect and/or minimize data errors. While NVM training is effective at calibrating NVM circuitry and implementing error correction, such training is also computationally expensive, and can require complex circuitry. Accordingly, there is a need in the art to develop error detection technologies and techniques for NVM that minimizes latency and complexity.